GUC has been delivering SoC design services on 0.5um to 28nm technology. Traditional chip implementation methodology hardly resolves the challenges of multi-million gates design, GHz operating frequency, noise coupling at deep submicron, IR drop, and design for manufacturing (DFM) requirements. In addition to hierarchical physical synthesis, clock tree synthesis, static timing analysis, and LVS/DRC, GUC’s advanced design flow, equipped with quick prototyping, formal verification, multiple power domain verification, cross-talk fixing and prevention, on chip variation (OCV), Critical Area Analysis(CAA), Lithographic Process Check (LPC), Virtual Chemical Mechanical Polishing (vCMP) check, etc., has been proven in hundreds of customers’ first silicon successes at deep submicron technology. On the other hand, GUC also delivers comprehensive design-for-testability (DFT) services including scan insertion, boundary scan, memory BIST, scan re-ordering, test pattern generation and compression, fault simulation services.
GUC offers full lines of IP internally or from third parties for SoC design. The IP portfolio includes high speed interfaces like 10G SerDes, XAUI, SATA, PCI-e and full service of ARM cores including Cortex and PLL, AD, DA in various technology nodes, just to name a few.
Besides, GUC provides SoC integration service from spec to GDSII or RTL to GDSII. GUC has successfully integrated complicated SoC and produced them in volume for hundreds of customer projects throughout the years while the ARM development platform has also expedited product prototyping.
- Memory BIST, JTAG, DFT, and ATPG
- IP customization and integration
- Design porting, FPGA to ASIC
- ARM Cortex 11, 9 series/ MIPS /Tensilica CPU RTL-to-GDSII customization and integration for different technology nodes
- IP Customization and integration service including digital, analog, and software IPs
- Customer prototyping build up service
- Customer project RTL design service