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PowerMagic® - Technology
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| Target |
Methodology |
Implementation and Verification |
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Leakage
Power
Reduction |
PSO |
Power Shut Down |
‧External power shutdown
‧Customized low leakage I/O pad power switch |
| Power Gating |
‧Coarse grain MTCMOS
‧Rush current analysis / decap cell insertion
‧Isolation cell insertion & verification
‧Data retention (FF and memory)
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| PowerSlimTM Library |
‧Multiple VT libraries swapping
‧Multiple channel length libraries optimization
‧Low leakage memory with deep-sleep mode
|
Dynamic
Power
Reduction |
Low Power CTS |
‧Clock gating clone / de-clone
‧Inverter tree & peak power mitigation |
| Multiple Supply Voltage |
‧Multiple voltage library characterization
‧Voltage islands with level shifter insertion |
| DVFS |
‧Power mode verification / optimization
‧Dynamic clock tree balance
‧Synchronization logic across power domains |
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| Mass production proven in 130nm/90nm/65nm/40nm designs |
Comprehensive low power solution
- Leakage power reduction
- Dynamic power reduction
- Low power design verification
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Proprietary low power methodology
- Power-aware DFT
- Yield-aware dynamic IR prevention
- Power gating rush current reduction
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- Low Power Design Success Story
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Process |
Gate Count |
Clock Freq. |
Application |
Methodology |
|
| 0.13um |
2M |
380 MHz |
Cell phone |
PSO+multi-VT+MSV |
| 90nm |
1M |
200 MHz |
DTV on cell phone |
PSO+multi-VT+power switch |
| 90nm |
2M |
200 MHz |
Cell phone |
PSO+multi-VT+customized IO |
| 65nm |
10M |
300 MHz |
Video |
PSO+multi-VT+low power library |
| 65nm |
1.5M |
200 MHz |
Cell phone |
PSO+multi-VT+MSV |
| 65nm |
8M |
300 MHz |
Cell phone |
PSO+multi-VT+DVFS+data retention |
| 65nm |
19M |
266MHz |
Smart phone |
PSO /MTCMOS+multi-VT+DVFS+data retention |
| 65nm |
11.3M |
266MHz |
Smart phone |
PSO /MTCMOS+multi-VT+MSV+data retention |
| 40nm |
22M |
266MHz |
Smart phone |
PSO /MTCMOS+multi-VT+MSV |
| 40nm |
11.6M |
266MHz |
Smart phone |
PSO /MTCMOS+multi-VT+MSV |
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