• Advanced Technology Design
 
 
  • Selected 65nm Project Summary
Service Type
 Process
Content
 Freq. (MHz) Application IP Status
N2G 65LP
10M gate
200+ memory
300 Video PLL, DAC, DDR
( Low Power )		 Production
N2G& DFT 65LP
~1M gate
~100 memory
 200 Video PLL, ARM,
Customized IO		 Chip Work
N2G& DFT 65LP
~1M gate
200 Mobile Customized ADC, DAC,
IO, LP Design		 Production
N2G& DFT 65LP
~2M gate
~100 memory
 200 Video PLL, ARM,
Customized IO		 Chip Work
N2G& DFT 65LP
5M gate
100+ memory
 300 GPS PLL, DAC, DDR,
Customized IO ,
ARM11(500MHz), LP Design		 Chip Work
N2G& DFT 65LP
2M gate
100+ memory
 300 Video PLL, DAC, ~20M eDRAM,
Low Power (MSV )		 Taped-out
N2G& DFT 65LP
~15M gate
~200 memory
 400 Video PLL, ARM, eDRAM,
ADC, DAC 		Taped-out
N2G& DFT 65LP
8M gate
200+ memory
 400 Video CPU/DSP Hardening,
MDDR, Low Power Solution		 Taped-out
N2G& DFT 65GP
50+M gate
300+memory [20Mbit]
2000+ Flip-chip IO
 400+ Networking SerDes, HSTL,
SFI-5.1/4.2 (3.125Gbps/lan),
XAUI 7 Blocks		 TPD: Q4/2008
             
 

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