• Low Power Solution
 
Low Power Design Platform
Target Methodology
 Implementation and Verification
Leakage
Power
Reduction		 PSO Power Shut Down
 ‧external power shutdown
‧customized low leakage I/O power switch
Power Gating ‧coarse grain MTCMOS
‧rush current analysis / decap cell insertion
‧isolation cell insertion & verification
‧data retention (FF and memory)
Multi-VT
 ‧multi-VT libraries optimization
Dynamic
Power
Reduction		 Low power CTS ‧clock gating clone/de-clone
‧inverter tree & peak power mitigation
Multiple Supply Voltage ‧multiple voltage library characterization
‧voltage islands with level shifter insertion
DVFS
 ‧power mode verification/optimization
‧dynamic clock tree balance
‧synchronization logic across power domains
     
Mass production proven in 130nm/90nm/65nm designs
Over 30 chips tape-out successfully
Comprehensive low power solution
  • Leakage power reduction
  • Dynamic power reduction
  • Low power design verification
 Proprietary low power methodology
  • Power-aware DFT
  • Yield-aware dynamic IR prevention
  • Power gating rush current reduction
 
  • Low Power Design Success Story
Process Gate Count Clock Freq. Application Methodology
 Status
1P6M, 0.13um 2M 380 MHz
 Cell phone
 PSO+multi-VT+MSV Mass Production
1P6M, 90nm 1M 200 MHz DTV on cell hone PSO+multi-VT+power switch
 Mass Production
1P7M, 90nm
 2M 200 MHz
 Cell phone PSO+multi-VT+customized IO
 Risk Production
1P7M, 65nm 10M 300 MHz
 Video PSO+multi-VT+low power library
 Risk Production
1P6M, 65nm 1.5M 200 MHz Cell phone PSO+multi-VT+MSV Risk Production
1P7M, 65nm 8M 300 MHz Video PSO+multi-VT+DVFS+data retention Q4/2008
           
 

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