• News Release
Global Unichip Adopts Synopsys Test Solution To Achieve Higher SoC Test Quality
Advanced Delay Test Capabilities in TetraMAX Improve At-Speed Test Quality
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   MOUNTAIN VIEW, Calif.September 27, 2007—Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that Global Unichip Corporation (GUC; TW:3443), a leading system-on-chip (SoC) design foundry,has adopted the Synopsystest solution to further improve SoC test quality. Employing Synopsys’ TetraMAX?automatic test pattern generation (ATPG) technology, GUC can strengthen the quality of its at-speed test solution and reduce return material authorizations (RMAs), also referred to as test escapes. GUC also intends to utilize Synopsys’ DFT MAX scan compression solution to reduce the test time associated with the increased design complexity and pattern counts inherent in at-speed test methodologies.

   DFT MAX automates the creation of scan compression circuits on-chip that substantially decrease the amount of data and time required to test digital designs. After a thorough evaluation, GUC selected DFT MAX because the tool exceeded GUC’s compression goals with only a modest level of effort required to integrate it into the company’s existing design flows.

   “At GUC, we rigorously test each product to ensure it meets our high quality standards,” said Louis Lin,senior director of Design Service at GUC. “As our design complexity increased and our manufacturing process shifted to 90- and 65-nanometers, delay testing became mandatory to enhance test coverage. By adopting the TetraMAX at-speed test solution, we improved test quality for several projects. In addition, we used DFT MAX scan compressionto reduce test data volume by more than 90 percent on several designs, and the compressed patterns were later successfully applied on our testers to verify working silicon. Itwas easy to get DFT MAX working with little impact on our delivery schedulesand we are impressed with the test results.”

   DFT MAX’s gates-only implementationhas minimal area impact on designs. By avoiding the use of complex sequential state machines for compression/decompression, the adaptive scan architecture disperses test logic throughout the design, alleviating wirerouting congestion and reducing silicon area overhead cost.

   “DFT MAX and TetraMAX together deliverthe most advanced EDA technology to achieve high testing quality,” said Gal Hasson, senior director of Synthesis and Test Marketing at Synopsys. “Synopsys’ test solution has proven to be of tremendous value to IC design service providers like GUCwhich differentiate themselves based on the timely delivery of highly reliable solutions.”

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