Hsinchu, Taiwan-Aug. 6, 2009- Global Unichip Corp. (GUC; TW: 3443), the world’s leading SoC Design Foundry, announced its Gbps level high speed production-proven total solution. The total solution includes comprehensive IP portfolio, ASIC implementation, chip + package co-design, and production testing solution. With this total solution, GUC has successfully helped customers achieve first silicon success in high speed networking, video processing, and mobile handset products.

Consumer and communication ASIC markets generally require Gbps high speed data interfaces, such as DDR2/3, PCI-e, SATA, USB3.0, XAUI, and 10G SERDES. However, product managers constantly run into challanges with the Gbps design, including signal integrity, bus skew control, system jitter compensation, power delivery network, and overall power reduction. Traditional ASIC implementation methodology can not effectively address all these challenges, due to additional electrical effects that need to be taken into consideration. These electrical effects include network resonance, transmission line effects, and insertion loss, among others. If the upfront implementation and production test scheme are not properly planned, the debugging process for the finished chips mandates extended development time and inevitably,  delays time to market.

"The Gbps level high speed total solution lowers our customers’ risk of  high performance ASIC design projects when partnering with GUC.” said Jim Lai, president and COO of GUC. "ASIC design projects can have a predictable timeline to success with GUC’s total solution. Our customers consistantly enjoy shorter time to market, and thus higher profit margins with this production proven process.”

GUC’s high speed interface design flow ensures all the aforementioned challenges are resolved at early stages in an ASIC design cycle. The package substrate design follows immediately after chip’s floorplan is finished. This allows the packaging model to be referenced by ASIC designers in order to verify the design specifications at earlest possible stage.

GUC’s recent success on in-house TSMC 40nm G process PCI-e Gen2 IP also demonstrates a significant milestone in this high speed total solution. The PCI-e Gen2 IP has been validated in the data rate that ranges from1Gbps to 6.25Gbps, while it consumes less than 100mW per lane. Furthermore, GUC plans to unveil a series of Gbps interface IP solutions, including DDR2/3, SATA, USB3.0, XAUI, and 10G SERDES by the end of 2009, providing GUC’s customers with a complete high speed design solution from IP to chip implementation, package and board design.