Design For Testability

Design For Testability (DFT) refers to those design practices that assist designers to reduce cost of test pattern generation, enhance fault coverage, and hence reduce defect levels at mass production. GUC’s DFT methodology provides a complete solution including RAM BIST, ROM BIST, at-speed RAM BIST, regular scan, AC scan, scan compression, boundary scan (JTAG), and ATPG, to achieve ultra-high test coverage.

Advanced DFT SolutionAdvanced DFT Solution

 

Success Story

ProcessGate CountApplicationDFT Feature
16FF+ 50M CoWoS/HBM 

DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1500

IEEE 1149.1/1149.6, HBM RAM BIST, HBM interconnection test

16FF+ 100M AP SoC DC/AC Scan, Scan Compress, @speed MBIST
28HPC 240M Networking

DC/AC Scan, Scan Compress, @speed MBIST, SerDes AC Scan, IEEE 1149.1, eFuse Test, Thermal sensor test

28HPC 6M UFS Controller

DC/AC Scan, Scan Compress, @speed MBIST, M-PHY DC Scan, IEEE 1149.1/1149.6, Power switch test

28HPC 15M SSD

DC/AC Scan, Scan Compress, @speed MBIST,  DDR3 DC scan, loopback test and BIST,IEEE 1149.1/1149.6, PCIe-G3 DCscan, loopback test and BIST, ARM DC/AC scan and MBIST, ONFI DC scan and BIST, eFuse Test

28HPM 100M SSD DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe loopback, DDR loopback, Thermal sensor test
28HPM 20M WiGig DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe loopback test, AFE loopback test, Thermal sensor test
28HPM 50M DSC Application DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1,
PCIe loopback, DDR loopback
40LP 20M Cellular BB DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, Power switch test, USB 2.0 DC Scan, DLL PHY DC Scan, eFuse Test, ADC Test, Codec DC Scan and loopback test
40G 60M LTE Baseband DC/DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1,
SRAM repair
40EP 10M Display DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1,
eDRAM repair