GUC multi-die interLink (GLink) IP

 

GUC multi-die interLink (GLink) IP provides world's best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a package for applications such as High Performance Computing, Data Center, Artificial Intelligence and Networking.


The IP utilizes single-ended DDR clock forwarding parallel bus interface with TSMC's RDL-based InFO (Integrated-Fan-Out) or CoWoS (Chip-on-Wafer-on-Substrate) up to 8/16Gbps per lane which consumes only 0.26pJ/bit. One slice has 32 full-duplex lanes and one PHY has 8 slices with 2/4Tbps maximum bandwidth.

 

 

 

GUC multi-die interLink (GLink) IP

Part. No Process Description Readiness Download
IGAD2DY01A 5nm Die to Die Interface PHY 2020Q4 -
IGAD2DX01A 6nm/ 7nm Die to Die Interface PHY V