Advanced Technology Design
  • 10nm DDR3/4 testchip tape-out in 2015’Q3
  • 16nm customer project tape-out in 2015’Q3
  • 16nm HBM solution with 2.5D interposer tape-out in 2016’Q1
  • 16nm DDR3/4 testchip tape-out in 2013'Q4
  • 20nm Soft Error Rate testchip tape-out in 2013'Q1
  • 28nm mass production since 2014

 

Tape-out Record :  > 200+ project tape-out from 2010 to 2016H1 

 

Selected 16nm / 28nm / 40nm Project Summary
ProcessGate CountApplicationKey Feature
N16FF+ 50M HBM Solution HBM Ctrl & PHY, 2.5D Interposer
2GHz CA72 hardening
N16FF+ 100M AP SoC TestChip NoC design, DVFS
PoP(3.0 and 4.0) package
CPU, GPU hardening
N16FF+ 50M Computing Engine  PLL, N16 ESD device
28HPC 240M Networking  2-level hierarchical P&R
SerDes, PCIE, LVDS, Efuse, Thermal/PM
SRAM 11K instance
28HPC 45M Networking 2-level hierarchical P&R
SerDes, PCIE, Efuse, Thermal/PM
28HPC 6M UFS Controller Power Shut Off
MIPI M-PHY, Toggle IO/PHY, LDO, OSC, Thermal Sensor
28HPC 35M SSD Hierarchical design, Power Shut Off
PCIe Gen 3, ONFI
28HPC 15M SSD PCIe Gen 3, ONFI, Thermal Sensor, eFuse
Power Shut Off
28HPC 100M SSD Hierarchical design, Power Shut Off
NoC design
PCIe Gen 3, DDR2/3
28HPC 20M WiGig Low power design
LVDS, PCIe, AFE
28HPC 217M Computing Engine VMK for variation management
Low voltage sign-off customization
28HPC 50M Digital Camera MTCMOS
Hierarchical design
PCIe Gen3 / USB 3.0, LPDDR2, CA7
40LP 37M Wireless Hierarchical design
ADC, USB, eFuse, DDR2/3
40LP 20M DTV Channel-lite hierarchical design
LVDS, XAUI, Serdes 10G
40LP 80M Industrial GPS Hierarchical design
DSP core @ 380 MHz
40G 60M LTE Baseband SRIO, SerDes, DDR2/3
ARM 926 hardening