Design For TestabilityDesign For Testability (DFT) refers to those design practices that assist designers to reduce cost of test pattern generation, enhance fault coverage, and hence reduce defect levels at mass production. GUC DFT methodology provides a complete solution including RAM BIST, ROM BIST, at-speed RAM BIST, regular scan, AC scan, scan compression, boundary scan (JTAG), and ATPG, to achieve ultra-high test coverage. |
Advanced DFT Solution
Success Story |
Process | Gate Count | Application | DFT Feature |
---|---|---|---|
7nm | 3.4B | HPC |
DC/AC Scan, HBM interposer test, MBIST, IEEE 1149.1/1149.6, Fail core identification |
7nm | 2.75B | Networking | DC/AC Scan, Fail core testing for logic redundancy, MBIST, TCAMBIST |
12nm | 1.25B | AI | DC/AC Scan, Ultra-scan, @speed MBIST, SRAM repair |
12nm | 220M | Camera | DC/AC Scan for 800+ clock domains, @speed MBIST |
16nm | 1B | HPC |
DC/AC Scan, HBM interposer test, @speed MBIST, SRAM repair |
16nm | 20.1M | AI | DC/AC Scan, @speed MBIST, System BIST, IEEE 1149.1/1149.6 |
28nm | 71M | Networking |
DC/AC Scan, @speed MBIST, System BIST,SRAM hard/soft repair |
28nm | 407M | AI | DC/AC Scan solution for 350+ tiles, Scan Compress, One chain for diagnosis, @speed MBIST |
28nm | 240M | Networking |
DC/AC Scan, @speed MBIST, SerDes AC Scan, IEEE 1149.1, eFuse Test |
28nm | 15M | SSD |
DC/AC Scan, MBIST, DDR/ PCIe/ ONFi/ eFuse |
28nm | 100M | SSD | DC/AC Scan, MBIST, IEEE 1149.1, PCIe/ DDR loopback, Thermal sensor test |
28nm | 20M | WiGig | DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe loopback, AFE loopback, Thermal sensor test |
28nm | 50M | DSC | DC/AC Scan, Scan Compress, @speed MBIST, IEEE 1149.1, PCIe/ DDR loopback |
40nm | 20M | Cellular BB | DC/AC Scan, MBIST, IEEE 1149.1, Power switch test, USB/ eFuse/ Codec/ ADC |
40nm | 60M | LTE Baseband | DC/DC/AC Scan, MBIST, IEEE 1149.1, SRAM repair |
40nm | 10M | Display | DC/AC Scan, MBIST, IEEE 1149.1, eDRAM repair |